Mendocino

Wednesday, July 15, 2009

The Mendocino Celeron, launched 24 August 1998, was the first retail CPU to use on-die L2 cache. Whereas Covington had no secondary cache at all, Mendocino included 128 kiB of L2 cache running at full clock rate. The first Mendocino-core Celeron was clocked at a then-modest 300 MHz but offered almost twice the performance of the old cacheless Covington Celeron at the same clock rate. To distinguish it from the older Covington 300 MHz, Intel called the Mendocino core Celeron 300A.[6] Although the other Mendocino Celerons (the 333 MHz part, for example) did not have an A appended, some people call all Mendocino processors Celeron-A regardless of clock rate.

The new Mendocino core Celeron was a good performer from the outset. Indeed, most industry analysts regarded the first Mendocino-based Celerons as too successful—performance was sufficiently high to not only compete strongly with rival parts, but also to attract buyers away from Intel's high-profit flagship, the Pentium II. Overclockers soon discovered that, given a high-end motherboard, the Celeron 300A could run reliably at 450 MHz. This was achieved by simply increasing the Front Side Bus (FSB) clock rate from the stock 66 MHz to the 100 MHz clock of the Pentium II. At this frequency, the Mendocino Celeron rivaled the fastest x86 processors available.[6]
At the time on-die cache was difficult to manufacture; especially L2 as more of it is needed to attain an adequate level of performance. A benefit of on-die cache is that it operates at the same clock rate as the CPU. All other Intel CPUs at that time used motherboard mounted or slot mounted secondary L2 cache, which was very easy to manufacture, cheap, and simple to enlarge to any desired size (typical cache sizes were 512 kiB or 1 MiB), but they carried the performance penalty of slower cache performance, typically running the FSB at a frequency of 60 to 100 MHz for motherboard mounted L2 cache. The implementation of the Pentium II's 512 kiB of L2 cache was unique at the time, comprising moderately high-performance L2 cache chips mounted on a special-purpose board alongside the processor itself, running at half the processor's performance and communicating with the CPU through a special backside bus. This method of cache placement was expensive and imposed practical cache-size limits, but allowed the Pentium II to be clocked higher and avoided front side bus RAM/L2 cache contention typical with motherboard-placed L2 cache configurations.[7]

Over time, newer Mendocino processors were released at 333, 366, 400, 433, 466, 500, and 533 MHz. The Mendocino Celeron CPU came only designed for a 66 MHz frontside bus, but this would not be a serious performance bottleneck until clock rates reached higher levels.

The Mendocino Celerons also introduced new packaging. When the Mendocinos debuted they came in both a Slot 1 SEPP and Socket 370 PPGA package. The Slot 1 form had been designed to accommodate the off-chip cache of the Pentium II and had mounting problems with motherboards. Because all Celerons are a single-chip design, however, there was no reason to retain the slot packaging for L2 cache storage, and Intel discontinued the Slot 1 variant: beginning with the 466 MHz part, only the PPGA Socket 370 form was offered. (Third-party manufacturers made motherboard slot-to-socket adapters (nicknamed Slotkets) available for a few dollars, which allowed, for example, a Celeron 500 to be fitted to a Slot 1 motherboard.) One interesting note about the PPGA Socket 370 Mendocinos is they supported symmetric multiprocessing (SMP), and there was at least one motherboard released (the ABIT BP6) which took advantage of this fact.

The Mendocino also came in a mobile variant, with clock rates from 266, 300, 333, 366, 400, 433, 466, 500, 533, and 600 MHz.

In Intel's "Family/Model/Stepping" scheme, Mendocino CPUs are family 6, model 6 and their Intel product code is 80524. These identifiers are shared with the related Dixon Mobile Pentium II variant.